Senior Microelectronics Design Engineer

Job Overview

This job announcement will be accepting candidate submissions until 10 October 2025.

OPEN TO CURRENT AFRL CIVILIAN EMPLOYEES ONLY.

The AFRL Sensors Directorate seeks to hire a motivated and experienced senior-level Electronics Engineer (0855) to serve as the Senior Microelectronics Design Engineer in the Advance Packaging Section (AFRL/RYDMP) in the Aerospace Components & Subsystems Division (AFRL/RYD) of the Sensors Directorate (RY) in the Air Force Research Laboratory. 

This position is open to candidates currently at the DR-02 or equivalent level eligible for promotion and current DR-03 or equivalent level candidates for reassignment. This position will be filled at the DR-03 level and is located at Wright-Patterson Air Force Base in Dayton, Ohio.

Your application WILL NOT be considered if all required documents are not submitted. See the list of required documents at the bottom of the announcement.

Position duties include, but are not limited to:

• Lead Digital engineering/twin methodologies in support of Program of Records
• Lead Digital IC design, ASIC, FPGA, microelectronics assurance in support of mission-critical research
• Knowledge of problems and solutions associated with modern hardware security and trust
• Applies expert knowledge and advanced engineering methods, theories, concepts, principles and processes to support the mission of proving options for programs to implement various levels of trust and assurance into their systems
• Oversees in-house and contractual programs ranging from basic research and exploratory development of advanced component demonstration efforts
• Builds coalitions and interacts internally and externally to foster collaborations, customer interactions and an environment of technology exploitation
• Actively engages organizational planning activities within the Branch, Sensors Directorate, Air Force, DoD, and other governmental agencies and provides input into future requirements and roadmaps
• Acts as a senior representative, technical and programmatic focal point to customers and partners on all assigned program-related activities
• Plans and manages both unclassified and classified research and development

Telework

Yes, this position is eligible for situational telework; as determined by agency policy

Eligible for a Referral Bonus?

No

Required Qualifications

• US Citizenship
• Must be able to obtain/maintain a Top Secret clearance with access to SCI and SAP clearance as condition of employment
• This is a drug testing designated position. The incumbent will be subject to random testing.
• Applicants must have at least one (1) year of specialized experience at the next lower grade, DR-02 or equivalent in other pay systems.  Specialized experience includes digital IC design, ASIC/FPGA development, and microelectronics assurance to proactively identify and mitigate vulnerabilities; applying advanced digital engineering techniques to lead the future of R&D in DoD platforms; and program management on DAF R&D efforts.
• Applicants must be able to meet the OPM Qualification Standards of the position being filled.  Positions will be filled using the following OPM occupational series:
• All Professional Engineering Series (0855): 
• https://www.opm.gov/policy-data-oversight/classification-qualifications/general-schedule-qualification-standards/0800/files/all-professional-engineering-positions-0800.pdf
• Possess a professional science or engineering (S&E) degree in a relevant technical field, from an accredited (or ABET accredited for engineering) academic institution
• This position is an Acquisition Professional Development Program (APDP) position requiring Tier 2 (Practitioner) Non-Critical certification in Engineering and Technical Management (N). Selectee will have 5 years to complete certification requirements and must have 4 years of experience to become fully certified.
• Selectee is required to submit annual Confidential Financial Disclosure (OGE Form 450).

Desired Qualifications

• Experience with executable test plans and coverage-driven verification
• Experience with IP license agreements, DIB partnerships, and government contract management
• Experience in digital engineering/twin, microelectronics verification, and assurance methodologies
• PhD in Electrical Engineering or related field
• Strong project management skills with experience tracking and managing cost, schedule, and performance
• Extensive experience planning, budgeting, developing, and executing research and advanced development efforts
• Strong communication and interpersonal skills to engage with program managers and senior leaders

When uploading documents please utilize the naming convention listed below. The Requisition Number is located at the bottom of the announcement.

• Resume (PDF): Req No_23460_Last Name_First Name_Resume
• Transcript: Req No_23460_Last Name_First Name_Transcript*
• SF-50: Req No_23460_Last Name_First Name_SF-50

*If uploading multiple transcripts, naming convention should include "Transcript BS" or "Transcript MA" as applicable.

Required documents include:

• Federal resume with relevant start and end dates in MM/DD/YY, per experience.
• Unofficial Transcripts Required
• Most recent SF-50 for current federal employees; redact all PII

Requisition Number: 23460

Series

0855